The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
As the scaling of semiconductor chips decreases and the density of circuitry and devices within the chip increases, testing such devices becomes increasingly important but also more difficult. One inherent attribute of semiconductor chips that makes testing difficult is the existence of capacitance structures within the chip. In a normal test chip, capacitance structures are relatively large because the parasitic capacitance contributed by pads, metal leads, and probes are in the order of picofarad (pF). The capacitance added to devices within a semiconductor chip is detrimental to the design, testing, and analysis of semiconductor chips because it can negatively affect the ability to obtain accurate measurements, such as capacitance-voltage (C-V) measurements, from devices within the chip. As technology scales, the capacitance of devices in the chip becomes more important, requiring regular monitoring of capacitance for accurate analysis of the devices.
One example useful method for testing semiconductor chips includes using probe cards. Probe cards are used to probe devices within the semiconductor chip for testing purposes, such as to determine if the devices meet design specifications. However, probe card testing makes parasitic capacitance cancellation extremely difficult on the same structure. The addition of a probe to the semiconductor device also adds to the capacitance of the device provided by the pads, metal leads, and other circuitry in the chip, making the parasitic capacitance even greater. The parasitic capacitance characteristics of semiconductor chips is a hindrance to the furthering of semiconductor device technologies.
SUMMARY OF THE INVENTION
The present invention is directed to a method and system for testing a semiconductor device involving the detection of parasitic capacitance to improve testing, designing, and debugging semiconductor chips. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor chip is analyzed. A test structure having a device, at least one pad, and at least one metal lead connecting the pad to the device is formed in the chip. A dummy structure is formed having a structure that is nearly identical to the test structure except for a gap in the metal lead to the device, wherein the gap disrupts the continuity to the structure. The dummy structure is probed and the parasitic capacitance of the dummy structure is determined. Using the determined parasitic capacitance to cancel out the parasitic capacitance of the test structure, the semiconductor chip is analyzed.
According to another example embodiment of the present invention, a system is arranged to test a semiconductor chip having a test structure and a dummy structure. The system includes a first probe adapted to measure the parasitic capacitance of the dummy structure. A second probe is adapted to couple to and analyze the test structure using the measured parasitic capacitance from the dummy structure.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not necessarily to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.